how to measure fpga execution time

[BradNC]

Howdy--

I'm hacking through my first FPGA project without yet having the hardware on hand, and I find I could answer a lot of my own questions if I could predict what the execution time (ticks, mSec, whatever) of bits of my code will be.  Running FPGA VIs on the Dev Computer with built in tick counters does not seem to be the proper way to go.  Is it possible to know the execution time of FPGA code before compiling and running it on the target?

If it matters to anyone, my context for the question is a situation where a 10 uSec loop is imposed by the sample time of my hardware (cRIO 9076, with a couple of 100 ks/S I/O cards), and I'm trying to figure out how much signal processing I can afford between  samples.

Thanks everyone, and have a great day.

[Drew_T · Accepted solution]

bcro,

You can look into cycle accurate simulation, which would give you a better understanding of how your code will work.  More information can be found here: http://zone.ni.com/devzone/cda/tut/p/id/12917

As a rough measure, you can estimate that simple functions will take one tick to execute.  However, there is not list of what is and is not a simple function.

You could also try placing code inside a single cycle timed loop (SCTL), which would then guarantee that all of the code in the loop will execute in 1 tick.  However, if you are doing a lot of operations or trying to acquire an analog input, this will fail compilation.

[BradNC]

Nice.  Thanks a bunch Drew.  Cycle accurate simulation is good to know about...I'll see what I can do with that until the hardware gets here.