manchester Clocking

[Shep_Ametek]

I am trying to Toogle a clock line for a full period to set a manchester enable communication. I am using a PXI-7813R  that with Clock 9 bit address binary array to the UUT.

There are a couple of articles on the NI Web site.  One Doc - 2824 indicates converting bytes to half bytes. I do not understand the concept right now.

I have attached screenshots of the Doc-2824 and my address control vi.

Any assistance on getting the Clock Line to work as a full period before grabbing the next bit in the array would be appreciated.

Thanks,

Greg

[tbob]

First of all, your images are hard to read.  Second, your images are hard to read because they have been shrunk from normal size because normal size is way to big.  Third, you are using sequence structures.  BAD idea.  Learn about modular programming.  Learn about state machines.

I suggest you search for state machines on NI website or on this forum.  Re-write your code in modular format.  Use subvi's instead of having everything in one vi.  By breaking functions down into subvi's, you will greatly simplify the code, make it more readable by others, and it will be easier to troubleshoot.  You can troubleshoot one subvi at a time, which is much easier than trying to troubleshoot a gigantic monster program.

After you do this, then re-post your code and ask specific questions about your problems.

[Shep_Ametek]

I was using the recommended structure for FPGA from NI Technical Support.   Does State Machines  work for FPGA Based code?

[tbob]

Sorry, I am not familiar with FPGA.  You probably can't write a state machine in LV-FPGA.  Someone else will have to take over.

[David_L]

A state machine consists of a While loop, case structure, and enum control, all of which are allowed on FPGA.  Therefore, there should be no problem for using state machines on LabVIEW FPGA code.  

As for your original question, I am confused as to what you are trying to accomplish.  The manchester encoding example is not something I'm familiar with, so maybe you can clarify your question by generalizing it for basic FPGA.  Sorry for not being much help here. 

[Shep_Ametek]

Manchester Communication is an XOR of both the data  and the clock. It seems the Data Period is twice the Clock period. If Positive Clock Edge could be considered active; the Negative Clock Transistion happens half way thourgh the data pulse period. This nullifies the negative clock transistion.  I am looking for a good way to recreate this negative clock edge null.  Currently, I have set up a Number to Boolean array then linked Array Bit 0 to Doubled Array Bit 0 & Bit 1, Array Bit 1 to Doubled ARray Bit 2 & 3, etc.  I set my for loop to 18 verses 9 iterations so I get the negative clock transition without changing the array data.

The clock is based on 200 Tick Timing Delay and a boolean false input going to an invertor and shift register as part of the for loop (based on 40MHz FPGA Clock).

See http://en.wkipedia.org/wiki/Manchester_code

Thanks,

Greg

[David_L]

I still am unfamilliar with the algorithm other than 30 seconds in the wikipedia article, but it seems like you could simply read the original data, XOR it with the clock and output this to the manchester.  If you run this in a Single Cycle Timed loop your manchester data will output an edge whenever your clock signal or data signal produces an edge.  Does this not work?

 

[Ben]

It has been years since I had to read Manchester encoding But i thought there was at least one clock transition for every bit cell time and there was an extra transition in the midle if the bit was set.

So half way between a rise or a fall you will se a transition for all "1"s but not for "0"s. Or am I mixint thae up with MFM?

Ben