Rif.: FPD link using PXI-1483

[LuigiM]

Hi,

in order to test if DUT's circuitry is working as expected, we need to grab video data (images) from its FPD link interface (3 LVDS pixel data lines + 1 LVDS clock line).

We are evaluating the use of PXI-6562 LVDS HS-DIO but even if the clock is 85MHz at maximum the data lines are sampled at 7 times the clock then these rise up to 595Mbps.

So we are asking if the NI-1483 can be used for this purpose through specific modification of FPGA code.

Can anybody give us a support on this?

There could be other solutions?

Thank you in advance for your reply.

Sincerely

[LuigiM]

I forgot to mention also the 6585 and 6587, for the first one the data rate issue is the same as for 6562, for the second one it reach 1Gbps but with only one DDC port (two ports could be better for multi DUT testing) and of course it is necessary to write all the FPGA code for image reconstruction wrt the 1483.

Many thanks for any suggestion.

Sincerely

[micahmcc]

Hi Luigi,

I am not too familiar with the 1483R. It is a device that is meant to be used with 'smart cameras' and has special I/O for configuring the camera and other smart-camera specific features. Based off your required clocks, the 1483R should be able to keep up with one LVDS line, but you will be at the maximum "serialized camera link cable transmission rate".

Per the 1483R specs:

"Pixel clock frequency range...................................20 MHz to 85 MHz
...This value corresponds to the serialized Camera Link cable transmission rate of 140 to 595 MHz"

Correct me if I am wrong, but your number of 85MHz clock * 7 sampling rate = 595Mbits/s is for only 1 of 3 LVDS lines, so your total data throughput rate will be 595Mbits/s x 3 LVDS lines = 1,785 Mbits/s. 

That above leads me to believe the the 1483R will not work for your application (perhaps someone can confirm my thinking).

The 6587R, however, is 1 Gbit/s on each of its 20 LVDS channels. So this card could handle each LVDS line with room to spare. Not too mention it is also a digital I/O card (none of the smart camera features) so I feel you will have more flexibility. While this card has only one DDC connector, it is the only HSDIO card that can handle the rates needed for your application.

I would like to point out one of our partner's products - the AlfaMation Flexmedia VA-01 video analyzer. The VA-01 is a FPGA Adapter Module (FAM) much like the 6587 and 1483, however it is designed specifically for video acquisition with 25Gbit/s data rates aggregated across 8 LVDS channels. It also comes with a LabVIEW API so programming will be much simpler than building your own with an HSDIO card, and you will not have to reconstruct the image as the VA-01 API does that for you. However, the VA-01 bitfile that is loaded onto the FlexRIO will prevent you from doing any of your own programming on the FPGA (same as any bitfile). Therefore, any additional processing would need to be done on the host. This is typical and usually not an issue, but I want to bring it to your attention since you seem to be interested in FPGA programming (although that could be for lack of other options). Please refer to the datasheet for details of specs and functionality, and if it interests you - I would recommend contacting AlfaMation support for more info and pricing.

As for reconstructing your image on the FPGA, I don't see why that wouldn't be possible if you go with the 6587 however I have little experience with FPGA programming. I would recommend posting in the LabVIEW FPGA forum and explaining what you want to do in the FPGA and what kind of data types/rates you will be working with.

I hope this information helps!

[LuigiM]

Hi Micah,

thanks very much for your reply.

In our case the FPD-link is of only 3 LVDS data lines and 1 clock line (18bit-RGB) but with a 9:1 ratio on data lines (standard is 7:1 for total 21 bits) due to the fact that the DUT uses MAX9209 serializer in DC balanced mode (that inserts 2 more bits on each line) with a maximum clock of 34MHz.

I had understood from the 1483 DS that it works up to 85MHz clock with a rate of 595Mbps on each data line so I belived that was appliable for our purpose.

Could you confirm this fact?

Surely the 6587R is appliable for our purpose in any case but with a greater effort on LV FPGA development.

We will ask also Alfamation for the VA-01 in order to evaluate the products characteristics (the DS you suggest is less more than a brochure).

Our customisation req is a important point of view cause the system should also be able to scale on a multi DUT testing.

Sincerely

   Luigi

[micahmcc]

Hi Luigi,

I talked to a colleague who is more familiar with the 1483 and CameraLink.

First, I would like to correct myself - the 1483 is designed for interfacing with CameraLink, not smart cameras.

My colleague agreed that the 1483 will not work for your application. It is designed to interface directly with CameraLink and, when combined with IMAQ/Vision libraries, hides the details of the actual signals from the user so that you can just acquire frames. CameraLink and FPD-Link are different specs altogether. For starts, CameraLink (and therefore the 1483) is made for 7:1 and the libraries would have to be modified for 9:1. But beyond that, there are also electrical differences between the two specs, and even if you could modify the code to work as 9:1 and created your own extra enable signals required by the FPD-Link spec, you would have to build it all into a CameraLink connector to even be able to plug it into the 1483. 

As for the VA-01, the datasheet is definitely more marketing material than a spec document. I pointed you to it because that is about all the detail they offer on their site as they request you contact support or request a quote for more information. I would be sure to explain to them you are using FPD-Link and see what options they have available.

Unfortunately, your best bet is to find a third party seller that offers something native for FPD-Link (I would really check with AlfaMation) or create your own solution with FPGA. 

[LuigiM]

Hi Micah,

many thanks for your interest and your investigation.

I want to point out that basically also FPD-link 1 is 7:1 as CameraLink but in this case the serializer uses a DC balanced mode so it injects 2 more bits on each lines. Furthermore, from an electrical point of view, both these standards rely on LVDS so the compatibility is assured, of course the FPDLink uses 3 data lines + 1 clock, instead CameraLink uses 4 data lines + 1 clock and also 2 additionals data lines (slow speed) for camera control I/O.

So the modification of 1483 could be quite relevant but we can work on LV FPGA without problem but if it is necessary also to rewrite the 1483 CLIP on VHDL the thing is more complex.

On the other hand, after the proper LV FPGA code implementation, the image data can be linked easily to IMAQ without other code development.

Did you still think, by asking also to collegues, that this way is not feasible?

Sincerely