What is the timing relationship between the input MUX and the convert clock in DAQmx

[nwild]

My application needs long settling times for analog input.  I can slow down the convert clock so as to increase the interchannel delay but I would like to know more about the internal timing and the timing between the input MUX switching and the convert clock.  DAQ is USB-6225.

Thanks,

Neville

[Aaron O]

Hi nwild, 

Have you been using the DAQmx Timing property node AIConv.MaxRate to view the maximum conversion rate for the USB-6225? This example, Setting AI Convert Clock Rate for the Longest Settling Time in DAQmx, shows you how to set the convert clock to the maximum if you would like to do that.

To answer your question regarding "the timing between the input MUX switching and the convert clock":

Your convert clock defines how long it takes for the input MUX to switch. The convert clock should be the only timing that you should need to consider regarding the multiplexed inputs. Every rising edge of your convert clock will switch the MUX and take a sample on that channel. The amount of time you have to settle, will be the period of the convert clock.

M Series cards are designed to have fast settling times. Take a look at the M-series manual, pg. 4-7. This discusses considerations when acquiring multiple channels when they are multiplexed. Also, the section on Convert Clock Signal might be useful to you.

Regards,

Aaron

[nwild]

Thanks Aaron,

Yes I have read the M-series manual, inparticular the section  starting on page 4-7.  I do have high impedance sources, thermistors and soil moisture probes, which is why I was concerned.  Increasing the convert clock period certainly allows accurate measurements.  From your reply I assume that the conversion actually occurs at the end of the convert clock period, that is the falling edge of the convert clock.

Thanks for your help.

Neville

[Aaron O]

Hi Neville,

I wanted to clarify one thing in your last comment. The conversion doesn't occur on the falling edge of the convert clock if you specify for it to start on the rising edge (you can pick rising edge or falling edge). If the conversion is triggering off of the rising edge, then the sample starts at the rising edge. The driver chooses the fastest conversion rate possible based on the speed of the A/D converter and then allows for 10us of padding before the next channel is sampled. If the AI Sample Clock rate is too fast to allow for this 10 μs of padding, NI-DAQmx chooses the conversion rate so that the AI Convert Clock pulses are evenly spaced throughout the sample.

Hope that helps!

Aaron 

[nwild]

Hi Aaron,

What I am really trying to do is to get a clear understanding of the timing relationships of the various actions that occur when analog inputs are sampled.  I have been looking at some timing signals using a USB-6210.  The 6210 is in its default configuration and I have exported the following signals to PFI pins.

My observations:

AI Sample Clock is always a 50 ns positive pulse.  Time between pulses is determined by sample clock rate.

AI Converrt Clock is always a negative (inverted) 50 ns pulse, the first one of which occurs 100 ns after the AI Sample Clock.  The time between pulses is determined by the AI Sample Clock rate.

AI Hold Complete Event Signal is always a positive pulse, 220 ns wide and occures 180 ns after each AI Sample Clock pulse.

From your earlier reply, I understand that increasingn the AI Sample Clock period increases the settling time and my checks confirm that measurements become more accurate with a slower Sample Clock, but should not the AI Hold Complete Event Signal be more delayed with respect to the Convert Clock?  I expected that the AI Hold Complete Event Signal would indicate the end of the settling tiime, but the delay of this signal does not change with changing Sample Clock rates as I expectedt it would.

Sorry to nag about this but I am just trying to get a better understanding of how it all works.

Thanks for any help that you may be able to provide.

Neville

[Aaron O]

nwild,

I think that you might have misunderstood about the sample rate and conversion rate relationship. Decreasing the sample rate will not decrease the conversion rate (unless you change the conversion rate using a property node). The driver chooses the fastest conversion rate possible based on the speed of the A/D converter and adds 10 μs of padding between each channel to allow for adequate settling time. This means that the multiplexed samples will all be close to the sample clock's edge (especially as you slow down your sample rate).

The AI Hold Complete Event signal generates a pulse after each A/D conversion begins. The AI Hold Complete Event is designed to signal an external multiplexer to switch to the next channel. The polarity of AI Hold Complete Event is software-selectable, but is typically configured so that a low-to-high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed.

So think of it this way: Each pulse of the Complete Event signal represents the end of an A/D conversion. Since the signal pulses on every A/D conversion, the name can be misleading because one scan could include multiple A/D conversions if multiple channels are included in the scan.

Here is some additional reading if you are interested:

DAQmx Events

What Is the SCANCLK Signal, and How Do I Use It? (this is the deprecated name for the AI Hold Complete Event)

Let me know if this is unclear or if you have additional questions.

Take care,

Aaron

[nwild]

Hi Aaron,

Thanks for your patience.  My understanding of what the exported convert clock and complete event signal indicate:

Convert clock indicates the switching of the input MUX.

Complete event indicates the beginning of the A/D conversion.

Settling time is determined by the convert clock period, so if I increase the convert clock period I would expect that the A/D conversion, as indicated by the complete event signal, would start later after the convert clock pulse.  But, what I observe is that the complete event signal always occurs at the same time (180 ns) after the convert signal, irrespective of the period of the convert clock.

I started to look into this when I wanted to increase the settling time for my analog input measurements.  Increasing the period of the convert clock certainly has the desired effect but I'm confused by the fact that the dealy of the A/D conversion does not seem to change when the period of the convert clock is changed.

Thanks again,

Neville

[Aaron O · Accepted solution]

nwild,

You are correct in the observation that the hold complete event pulse happens 180ns after the convert clock rising edge, regardless of the period of the convert clock.

This is the process:

1. The Convert Clock generates a pulse to start the ADC conversion.

2. A set amount of time (in your case, 180ns) after the Convert Clock pulse, the Hold Complete signal pulses. This indicates that the data is "held" by the ADC. It is now OK for the MUX to switch to the next channel. It is important to note that the ADC conversion is not complete when the Hold Complete pulse happens. 

3. At this point, the MUX will switch and the device will wait for the next convert clock pulse for the start of the next conversion.

In summary, this means that when you change the Convert Clock signal period width, the Hold Complete signal will still pulse the same fixed amount of time after the convert clock signal edge. The Hold Complete signal is not a good indicator of settling time; the Convert Clock period width should be the indicator of settling time (which it sounds like you determined from you're previous posts). A good application for the Hold Complete signal would be for an application where there is an external multiplexer and the multiplexer needs a signal to indicate that it is OK to switch inputs.

I hope that helps clear up any uncertainties you have about how this works!

Regards,

Aaron

[nwild]

Hi Aaron,

I think the penny has dropped.  The Hold Complete Signal indicates that the MUX has switched to the next channel in the sequence and so the next channel has until the next Convert Clock to settle.  I've been thinking that all the settling and conversion took place between the Convert Clock and the Hold Complete Signal.  I now understand how the settling times for channels after the first channel are equal to the Convert Clock period.

There is still one thing which I don't understand: what is the settling time for the fist channel in a sample?  It seems that it can't be the Convert Clock period because the first Convert Clock always occurs 100 ns after the Sample Clock?

Thanks,

Neville

[Aaron O]

Neville,

You should think of the first channel's settling time as the delay between the Sample Clock pulse and the first Convert Clock pulse. By default, this delay is three ticks of Convert Clock Timebase. 

Regards,

Aaron