Engine Simulation Custom Device Feedback

[jamesy]

here are the files again in case they didnt load for some reason.

[0utlaw]

Hello James,

Please disregard my earlier post- I was misinterpreting the add-on's parser as well as the level at which the Engine Simulation bitfile was imported into NI VeriStand. Your original attachments are present, due to the larger file size they were still enqueued for virus scanning at the time of my last post.

In any case, it appears that the channels that are not being imported correctly have an extra blank space at the end of the channel (indicator) names (labels).  FI 2.TimeDuration, FI 3.TimeDuration, and FI 8.End Angle do not. 

[jamesy]

Great you were exactly right guys. I deleted the blank spaces at the end of the indicators and everything is now available in veristand. The Falling edge code i created also works great.

Question: How do i set the "ECUEvents.CyclesToFilter" ?

I dont see that in veristand. When i set it in labview and save the Vi, it is set to 0 when i re-open the Vi.

Oh and finally, i see an number of people on the forum asking about adding a timeout after no pulse has occured for one 720 degree cycle. Did you guys ever get the time to put something together?

This is something which i also need.

thanks,

james(y).

[StephenB]

you can just wire a constant to that on the block diagram

[jamesy]

Steven,

Do you have a suggestion as to how i would add the timeout. Looks like i cant use local variables as Labview pops up an error when i try to compile.

every 720 degrees i want to check if a falling edge flag was set high. then clear the flag. i used selectors to set the outputs to 0 if no falling edge flag was detected.

James.

[jamesy]

If i cant use locals then how can i detect if an event occured within the previous 720??? I have to remember the event somehow.

[jamesy]

here is my attempt. no errors in labview but it doesnt compile due to the locals

[jamesy]

I've now also attempted using a shift register and a queue. Both fail as they are not support in a single cycle timed loop.

Some direction or hints would be great.

thanks,

James

[jamesy]

I've made some progress on the timeout detection.

I decided to replace the single cycle timed loop  with a normal while loop. ( its a timed loop running at 5us)

I'm using a local variable to store if a falling edge was detected. ( FE Detected) I then check this local variable every 720 degrees.

I use a latch ( FE Latch) to store the current decision when the angle !=720.

The VI is called:

AES ECU Event Measurement - All Measurements FE local FPX.vi

Using ED1 as an example, Veristand reports:

ED1 Start angle ==1

ED1 End Angle == 1

ED1 Angle Duration ==1

ED1 Time duration == 0

I have attached my VIs. Some help would be appreciated.

James.

[jamesy]

Hello,

I've found an issue when running the AES HIL custom device at 3khz or above.

1-2 kHz looks fine.

I'm running on an FPGA, via pharlap.
I set the loop speed in Veristand as shown in the attached document.

Open the attached 4khz log:  Log File_09_52_30_AM_06_06_13 in the veristand TDMS file viewer.

Look at the crank and cam plots.  They should be perfect saw tooth waves, just like they are at 1khz.
Notice the instantaneous jumps in angle throughout the log. approx 40 degree jumps.

I can see that there are no "late errors" reported by the veristand system variables in the log.
However the crank and cam traces show some kind of delays.

I'm using the embedded data logger. The logs are stored on the pharlap target PC, I then download them to my host.