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03-09-2017 08:58 PM
Hey Ning,
Getting duty cycle and frequency through VeriStand's built-in implementation is a little tricky since by default it only exposes duty cycle. I failed to mention this in the Huazy response (I think it's in a couple of these other pages of the thread) but there's a good example online of how to get VeriStand to provide both. You can check it out here.
On another note, since PWMs are usually asynchronous anyway (depending on your synchronization concerns) I usually implement my PWMs with regular code and use the FPGA Custom Device to pull in my indicators for DC and Frequency. But that's likely overkill for what you're trying to accomplish, I'd recommend starting with the forum I linked above.
Hope that helps! --Ryan_S
03-09-2017 09:19 PM
Hi Ryan_S,
Thank you very much for your timely reply. I will try according to your prompts.
Best regards
Ning
03-24-2017 05:47 AM
Hey Ryan,
It's been a while since i've wrote you about generating Pwm with a variable Freq and DC on the fly. I can say that i'v understand how it's be done after Advanced PWM example, this i come to you for some explications about the yellew rounded paramters below (picture attched).
Also i would like to know if is it the same thing with the Pwm Inputs ? what means if we can variate the freq & Dc on the fly. you find also below a screen of a part of my Fpga personality code to have your opinion on it, and if there is a way to do it more better.
Thank you beforehand.
Best regards
08-14-2017 07:08 AM
Hi!
I need .fpgaconfig for NI myRIO and I got to know that I can build FPGA personalities using this tool. But the problem is I couldn't do it for myRIO. I really appreciate if any one has already built .fpgaconfig file of myRIO and help to build it or post it here!
Thanks in advance,
Harshavardhan
08-14-2017 04:04 PM
VeriStand on a myRIO? That doesn't make much sense...you're going to get horrible performance...
But you should be able to use the node to make your own .fpgaconfig and corresponding bitfile. It still shows up on the palette for myRIO, so it should work fine...follow the tutorial in the "Instructions for Use.pdf" attached on the download page for the add-on and it should work.
12-04-2017 08:57 PM
Does anyone know if this code base is still maintained? I believe I have a fix for bug #5 (although there is a workaround) I was curious as to the state of this code base.
04-18-2018 09:23 AM
Hi - I've got FPGA XML Builder Node with 144 channels. I need to delete some of the channels between the beginning and the end. How do I do that without deleting and recreating succeeding channels?
04-18-2018 12:18 PM - edited 04-18-2018 12:19 PM
Unfortunately there isn't an easy way to do that. The feature was never implemented.
The easiest solution I can offer is to change any unused inputs to Reserved_In_0 to Reserved_In_N and connect constants on the block, then similar naming for the outs, and just don't wire them to anything.
Then just don't use them within your sys def.
--Ryan_S
04-18-2018 03:29 PM
Thanks Ryan for timely reply. Makes sense. Unfortunately I'm trying to make my FPGA program smaller so it will on my device, so I do need to actually remove them. While I was waiting I did actually remove them the hard way and my FPGA now fits my device. Maybe something to put on the wish list, but I can see where the workaround would probably satisfy most people's needs. Do people not use this very much? Even with the work around, seems like this would be something folks would want to improve early on. Thanks anyway! Cheers!
04-18-2018 08:28 PM - edited 04-19-2018 09:19 AM
I tried to load the fpgaconfig file into a new veristand project and got the errors below. See attached.