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How to solve time voilation problem during compilation

There are the following mistakes at the end of compilation. Is there any suggestions to solve this problem? Thanks

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Message 1 of 3
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It's hard to say because you didn't attach your code or provide a screenshot of the loops that are failing timing. It looks like you might have placed a non-reentrant subVI inside multiple Single Cycle Timed Loops (SCTLs). Any subVIs inside SCTLs should be reentrant so that each loop has a separate (independent) copy of the IP core.  Otherwise, it's impossible to meet timing because you can't access the same resource in multiple places at the same time.

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Message 2 of 3
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If you are using SCTL, what is the loop rate of SCTL? Are you using pipelining technics or not?

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Message 3 of 3
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