Loop timing in FPGA

[A.A.K]

Hi All,

I am running my code on FPGA board (PXI 7813). I am using simple while loop for my pwm switching instances. The moment i try to replace my while-loop with a timed-loop it gives me error stating " it cant contain high throughput blocks from the FPGA module" . Moreover if i put normal loop delay it just doing funny things i.e not giving the required delay as calculated according to ticks/loop rule.

Can anyone pls help me with this.

Regards,

AAK.

[hiltech]

Have you isolated a specific high throughput block function which is causing the error?  Are any high throughput blocks in your SCTL not configurable for pipelining and input/output registers (ie. latency not configurable)?

[A.A.K]

Yes I have isolated it earlier. STCL also does not support "divide" (arithmatic function)  within the loop and that is part of my code. How can i tackle that ?

[hiltech]

do you have the option to reciprocate the value on the host side and pass the FPGA a value with new units through a front panel control?

[Ceslav]

Hi All,

just some thoughts on the subject:

1. Indeed there are some functions that can be used only outside SCTL as those require multiple cycles to execute. Division is one of such functions. The HT math functions also should be configured to match the execution mode of the loop, i.e., in or out of SCTL. Otherwise you get an error (it is also specified in the help).

2. I don't believe reciprocating on the HOST is an option, it will take more time to shift the data around than computing everything in the FPGA in a while loop and communicate the result through FIFOs or global/local variables.

3. I would not recommend using while loop for PWM generation. It is not accurate (even not necessary very deterministic) and the resolution you get is rather low. SCTL with HT math functions is the way to go in my opinion.

4. Typically, I break the code in smaller manageable parts and insert them into separate  SCTL (when possible). Increasing the rates of the separate loops independently can give you higher overall performance. Depending on the architecture, I would use FIFOs or global vars. to communicate in between the loops.

[A.A.K]

Hey Ceslav !

I did the exactly same what you suggested. It started working without any further errors but my switching within the timed loop is still very fast. I used a reduced derived processor and also increased the time period still i am struggling to slow it down. Pls advise.

Thanks,

AAK

[Ceslav]

Dear A.A.K

Probably, you should describe your problem in more details (a snippet of your code could help). Please, give some numbers, i.e., what is the expected PWM period, what is actual PWM period, what is the clock rate, etc.

Otherwise, I cannot provide any specific feedback.

Just to be sure, do you check the PWM waveform in simulation or on the actual hardware?