PWM in Co-simulation

[icedancer]

How to generate a PWM signal (200kHz) with 1ns rising and falling time in co-simulation? It seems that the original models don't work.

[BMac]

For a simple PWM with ON and OFF time programming like you might be looking for, this IP core my be what you want. Place the subVI in a Single-Cycle Timed Loop using a clock from 40 MHz to 200 MHz and connect the Output Boolean to the digital output line on the sbRIO GPIC.

https://decibel.ni.com/content/docs/DOC-2380

The physical rise and fall time will depend on what type of I/O you are using, as well as the termination resistance, characteristic impedance of the cable, and type of receiving digital input. For a discussion on this topic, see the thread below. The sbRIO GPIC half-bridge digital outputs (gate command signals) have a 100 Ohm termination resistance in series for compatibility with the impedance characteristics of common gate drivers such as Semikron SKiiP 3.

https://decibel.ni.com/content/docs/DOC-19216

Alternately, you can use the 3.3 V LVTTL lines on the sbRIO GPIC. There are 32 LVTTL lines available. These are raw FPGA input/output buffer lines, so you must be cautious not to damage the FPGA when using them. Unlike the half-bridge digital outputs, they do not include the half-bridge drivers necessary to directly connect to common gate drivers over a cable. However, they give you the full speed of the FPGA. For signal integrity reasons, you will want to add series termination resistors (typically 100 Ohms) to match the impedance of your cable. Alternately, you could use differential line drivers or other signal conditioning chips. For more information on this raw LVTTL I/O type, see the application note below.

http://www.ni.com/white-paper/13489/en