Large FIFO Elements Remaining

[Nealski]

Basically I'm using LabVIEW 2011, NI cRIO-9118 Chassis, NI cRIO-9014 Real-Time Controller, one NI-9205 module (for Displacement), three NI-9239 modules (for Acceleration), three NI-9236 modules (for Strain Gages), and one NI-9401 module (TTL for indicators).

I used flat sequence (just like the examples that I saw in the help) for  the FPGA VI with three while loops in one of the sequence. The first while loop is for the acceleration (NI-9239) with 13 channels for FIFO(1), the second while loop is for the displacement (NI-9205) with 12 channels for FIFO(2), and the third while loop is for the strain gages (NI-9236) with 25 channels for FIFO(3). All the while loops are inside one sequence.

Same as the examples, I used while loops for each FIFO for the Host VI. I have a total of four while loops in the Host VI, one for the commands and three for each FIFOs (1, 2 and 3). The programs runs and collects data but when you see the elements remaining for each FIFOs, it spits a large number meaning it might be losing packets of data for each FIFOs. I have use LabVIEW 8.5 and 9.0, but I never got any large numbers coming out of that indicator (FIFO elements remaining). What is causing it to spit our large numbers of FIFO Elements Remaining? Also in LabVIEW 8.5 and 9.0, I can go each FIFO properties (from the project tree) and select the DMA Channel (1, 2 and 3) for each FIFO. Meaning I can select DMA Channel 1 for FIFO 1, DMA Channel 2 for FIFO2, and DMA Channel 3 for FIFO3. LabVIEW 2011 doesn't give you that option so I'm not sure if it's automatically selecting the right DMA Channel respectively for each FIFOs.

[Allison_M]

Hi Nealski,

DMA Channels are handled internally by LabVIEW as of 2011, that is why you are no longer able to select it in the same way that you could in earlier versions of LabVIEW.
Regarding the large number of items remaining, do you get out of memory errors or buffer overflow? Does the number increase or stay relatively static? It sounds like you have this correctly implemented. When you say you have done it in earlier version of LabVIEW, were you using the same program on your FPGA or are you just saying that in similar programs you did not see this?

Hope this helps,

[Nealski]

 Hi Allison,

I'm getting the large "elements remaining" from the FIFO.Read (FPGA Interface Invoke Method) on the Host VI. The number increases up to a 1000 elements then comes back to smaller number, about 15.

The software program/application that I created using previous LabVIEW versions (8.5 and 9.0) is the same as the software program/application that I created now using LabVIEW 2011. Everything is the same except the number of channel is less than the previous one. It doesn't make sense because from the previous version, I never seen large elements remaining (maybe 15-45) and it has more channels than the latest.    

Thanks,

Nealski

[Allison_M]

Hi Nealski,

 If you are not getting an error or a crash then this is probably not a problem. The 'number of elements remaining' being called on the host VI is referring to the number of elements in the FIFO on the host side, not the FPGA side. The fact that it grows and then gets smaller is because the host VI loop is running much slower than the FPGA VI, so the FPGA might be loading elements into the FIFO one at a time 1000x faster than the host VI is reading from the FIFO, but the host VI will read chunks of data instead of single elements. This allows it to run at a lower loop rate. The fact that the number is larger than you have seen before can be related to a number of things such as an increased sample rate or processing on the host side is causing the loop to run slower (and therefore more data is being loaded into the FIFO before the host can unload it).

This is not unusual behavior, however if the size of the FIFO grows with time and continuously get larger then you will eventually have a memory error and this is a problem. If this is the case you have to increase the rate that the host takes data from the FIFO (possibly by reducing the processing time) or decrease the amount of data being loaded into the FIFO by the FPGA (by reducing the sample rate).

I hope that helps. 

[Nealski]

Thank you for the information and the suggestion.

How do you increase the rate that the host takes data from the FIFO or reduce the processing time?

Thanks.

[Allison_M]

Hi Nealski,

In order to increase the rate that the host takes data from the FIFO, you will need to reduce the the processing time by either introducing a faster controller or simplifying the processing done on the real-time host.