Use scan mode w/cRIO @ 200hz for 96 AI and 96 DOut channels?

[mak90]

I may be pushing the limits of the controller here, but I have 3 Ni9205 analog input modules, and 3 NI9476 DO modules and end result desired is to essentially monitor the 96 analog input channels and if their value exceeds some specified limit, open a relay (i.e. punch a Dout channel) :: all happening at 200hz.  I have never done any NI FPGA programming, and am in a bit of time crunch so I am using the 'Scan mode' option available with my cRIO9012 and 8.6.

Is this impossible with the scan mode, and if so do ya'll think I should just go nuts and try and figure out how to do this with the FPGA (keep in mind its only a 1M FPGA)...

Thanks for any assistance!

[jkurtw]

mak90,

The scan engine performance benchmarks will be helpful here: 

http://zone.ni.com/devzone/cda/tut/p/id/7792 

Table 2 shows CPU usage for performing PID on 80 channels (AI/AO pairs) at 100Hz, which uses 28.61% CPU. The CPU hits 100% usage at 399Hz for 80 PID channels.

At 200Hz and 96 channel pairs you will have significantly higher than 28.61% CPU, but I believe you will be well under 100%. 

Also, you mention that you have a 1M gate FPGA. Are you using a 9102 chassis? Because the FPGA logic for eight scan mode slots will not fit on the 9102 1M gate FPGA, you will need to go through a few additional steps to get scan mode support on the six slots you are using. This will require LabVIEW FPGA and a compile, but no FPGA programming.

1) Add an offline 9012 to your project

2) Add an offline 9102 to your project

3) Right-click on the Chassis item and select New » C Series Modules...

4) Add the modules you will be using

5) Right-click on the Chassis item and select New » FPGA Target

6) Right-click on the FPGA target and select New » VI

7) Save and compile the blank FPGA VI

When you compile this blank FPGA VI, it will suck in the logic to support scan mode in the slots that have modules under the chassis item.

Then in your RT VI open and run the FPGA VI before your read/write to any I/O variables. This will deploy the scan mode logic to the FPGA.

For more background info on this, check out this white paper:

The RIO Scan Interface Under the Hood 

http://zone.ni.com/devzone/cda/tut/p/id/7693 

Hope this helps!

Kurt 

[mak90]

Ok thanks for the info!

I am currently running my 96 ai and 96 do channels ok in a timed loop @ 10ms dt, with a slave lower priority loop taking snapshots of the data ( i only need to record data every 6seconds) - with the master loop at 10ms dt i.e. 100hz i'm still banging 100% cpu, so does that mean I need to do the FPGA trick you mentioned, or without the FPGA code you mentioned would nothing even work?

More concisely, do I absolutely have to do what you described with the FPGA for my desired result?

thank you!

[jkurtw]

Hi mak90,

If you already have scan mode working without doing what I described above, then you must have a 9104 chassis with a 3M gate FPGA, in which case you do not have to do the FPGA trick described above.

If you are already at 100% you may need to program this on the FPGA. Fortunately, your application is fairly simple and should be easy to program on the FPGA.

Before you take that route you can try a few things to optimize your code. 

First, try wiring all of your I/O variable (IOV) error clusters together so that they run sequentially, instead of in parallel, like the attached image. Because of some LabVIEW compiler details, they run a over twice as fast like this. (~8uSec vs. ~20uSec each)

One thing you can look at, to get an idea of how much CPU the I/O scan itself is taking, is to look at the time-critical CPU usage of your controller in the system manager when no VIs are running. This is the amount of CPU that the scan engine is using. See image attached. You can launch the system manager by right clicking on the cRIO controller and selecting Utilities » View in system manager. 

If you have a CPU usage of about 70% or higher, when no VIs are running, then you are not going to have much to work with and I would consider coding this app. on the FPGA.

Let me know what you find with this test. I am curious how much CPU your scan will use with that many I/O points at that rate.

Kurt

[mak90]

Wow first off I really appreciate the attention you're giving me on this !!

First of all, yes I have 9104 (3M) FPGA - sorry for the incorrect information there.  I also performed what you asked regarding the sequential wiring of the analog input channels. And I included screenshots of all the code, if you're THAT interested (I hope you are).

The most perplexing thing about all this, is that from time to time I get it working with ~65% CPU usage, then I come back after making slight changes and its bombing at 100% usage, and I even if I revert to the same parameters as before it still pegs 100% CPU?? I have yet to understand this. I can't believe that it's random.

Nevertheless the code shots which i provided, when run do not tax the time critical portion of the CPU hardly at all, and I don't know how you 'deployed' your variables and could see their voltage readings in system manager like that (to get your scan engine utilization value without any running VIs). 

So at this point I'm just trying to reach the magical combinations of timed loop timer-values(target) and while loop timers(host) that will allow me to run at 200hz without killing the CPU. Once I get there I'll probably lock it down. Unless you can help me make some sense of all this.

Once again, I appreciate your time in this-

jacob

[mak90]

Ok I feel foolish.

Immediately after posting, I decided to go crazy and wire all the DOutput shared variables sequentially like you suggested (i had only done the AI's before and hadn't noticed a big change so shame on me), and voila! after doing so I am running with 80% utilization and everything else is behaving as desired.  So I will consider this problem fixed for the moment - and chalk it up to the sequential wiring of the shared variables!

Thank you so much! I would have drown out here without that lifesaver-!

jacob

[jkurtw]

Sweet! 

Glad to hear you are up and running.

Kurt 

[jkurtw]

Oops... one more thing.

I just looked at your screen shots. I can't see your timing source, but make sure you use the Synchronize to Scan Engine timing source for your timed loops.

This will guarantee that you are not reading repeat data and that your loop executes each time the scan brings in new data. You can then use the dt input to specify how often to run (ever 5 scans instead of 1 for example).

If you don't use that timing source, your loop is basically running asynchronous to the I/O updates, so you could read the same data twice, or miss data.

If you are using a regular while loop, then you can use the  Synchronize to Scan Engine VI, in place of a wait, in the scan engine palette under Measurement I/O.

Just to be sure, are you setting the scan engine rate under the controller properties page? I noticed that your time-critical thread in the system manager is <1% but timed structures was 95%. This could mean your scan engine is running slow and you are reading the data repetitively with a fast timed loop.

Kurt 

[mak90]

Kurt you da man! Thanks for following up by looking at my crappy code!

You were absolutely right-  In all my ignorant hacking I had set the scan engine to something like 500ms (Doh!) But now, with the loops correctly synced to the scan engine, and the scan engine updating at 5ms, I'm only at like 50% cpu utilization! Sweet! You've been like a scan engine cRIO tutorial for me - thanks again

jacob

[jkurtw]

No problem. I am glad I could help out.

That is great that you are down to 50% CPU.

And your code is actually quite pretty. Did you do all that I/O wiring or did you use block diagram clean up?

kurt