What would the effect of setting the DMA FIFO depth before each read?

[mgerceker]

I am using a PXI-7813R FPGA board using a 3rd party API. I have been having a few issues while reading. I looked into their API code (LabVIEW) and realized that they have been setting DMA FIFO depth before each read from the FIFO. This apparently does not cause a catastrphic failure as the issues I have been observing are only transient in nature.

What kind of problems if any can this kind of operation cause or will it be ignored as the FIFO is already running?

Thanks....

[Ben_J1 · Accepted solution]

mgerceker,

   According to the help file this should be okay to do although I could see it being an issue if it is not properly set before running an operation. What kind of symptoms are you seeing?

Regards from Austin,

[mgerceker]

I have been seing extra/missing data points during reads, which may be due to many similar unfortunate programming issues. If I am not mistaken the right way to do this would be setting it up when I start the data collection procress after flushing the buffer and then leave it alone for the remainder of the process.

However I think the original programmer may have done this on purpose to keep the FIFO clean after each read to cover up other issues, which is very alarming. (Clearing the FIFO after each read in a continuous data collection routine does not seem to be very appropriate.)

I'd appreciate any other comments you may have on the issue.

Thanks.

[Ben_J1]

mgerceker,

   There are a lot of variables in situations like these. It sounds like you have found a good resolution but if something like this comes up again any time you can post up a screenshot of the code, the better the community can help you out.

Regards from Austin, TX,