cRIO-9082 DMA bandwidth between RT and FPGA

[JCC_(SK)]

Good morning,

I would like to know DMA bandwidth of cRIO-9082 between FPGA and RT? How many MB/s? I can not find answer on NI web page.

I know that there are 3 DMA channels but how fast I could send data from FPGA to RT memory?

What is optimal size of element in DMA channel? U8, U16, U32 or U64?

Hardware: cRIO-9082 RT

Software: LabVIEW 2012, LabVIEW 2012 FPGA

Best regards

 Peter

 CLA

[JCC_(SK)]

Response from NI UK support:

FPGA and RT (RAM) are connected by PCI bus.

Theoretical maximum is 133.3 Mbits/sec.

Normal transfer bandwidth is between 90-100 Mbit/sec.

[ThiCop]

Don't you mean 133 MB/sec or 1.06 Gbps as theoretical maximum of PCI?

[JCC_(SK) · Accepted solution]

Response from NI UK support and correction by ThiCop:

FPGA and RT (RAM) are connected by PCI bus.

Theoretical maximum is 133.3 MB/s.

Normal transfer bandwidth is between 90-100 MB/s.

[JCC_(SK) · Accepted solution]

Response from NI UK support and correction by ThiCop:

FPGA and RT (RAM) are connected by PCI bus.

Theoretical maximum is 133.3 MB/s.

Normal transfer bandwidth is between 90-100 MB/s.