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How to use PCI 6534 to perform pulsed pattern generation

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Dear friends, 

 

 

We are using PCI 6534 to do pattern output, software platforms are C++ and NIDAQmx.

 

The experimetal sequence is following:

 

(1) Output 400,000 samples (32-bit, so all channels are used) upon a trigger (start trigger);

     Rate: 3MHz; so the total pattern output lasts about 50 ms; Internal on-baord clock;

 

(2) Wait for a few seconds, typically 5s;

 

(3) Output the next 400,000 samples (32-bit) upon a trigger; the sample here is different from that of setp (1); 

 

 

(4) wait for a few seconds and output a new group of 32-bit 400,000 samples.

 

 

Now I have gone through the step (1), the code used are attached.



Do anyone have suggestions how to proceed?

 

Is it possible to load all the three groups of data array to the on-board FIFO, and use start-trigger and stop-trigger to start and stop the generation of three pulse groups? 

 

Or is it possible to use the two on-board FIFOs, when the 1st FIFO is output, load data from PCI to the 2nd FIFOand wait, and so on...?

 

Thanks a lot!

 

 

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Sorry, each 50ms pulse would include 150,000 samples in our case.
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I would recommend as you have defining the sample mode to be finite. Define the trigger parameters. Commit the settings into hardware by using the DAQmxTaskControl DAQmx_Val_Task_commit.  This allows for very efficient restarts. Then have the write, start, and stop commands within a loop. Each write within a case structure that defines which values to write to the buffer. 

You can also reference the following KnowledgeBase article 2MOESVN5 for examples using the double buffer but would require some modification to apply the third set of data.

Regards,
Glenn
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Thanks a lot, Glenn. I kind of underatnd what you mean, but for firm check, I have attached the core part of the modified program, could you have a look at it briefly and see if that is what you meant? 

 

I have two more questions regarding operation in this mode: 

 

(1) Our data set includes sample size of 32-bit and sample numer 150,000.  How long it would take to reload another set of samples to the on-board FIFO?  

 

(2) For the hardware triggering, under this circumstance we need three Low-to-High triggers to initiate the three outputs, right? How long would be the delay between the trigger edge and the time when the actual output start? 

 

 

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Solution
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Your DAQ process looks good,

Keep in mind, the data transfer process for output tasks. The data is created in the application buffer and transferred into the PC buffer then transferred into the onboard memory either by DMA or interrupt. PC buffer to on board memory is pretty consistent and you can reference KnowledgeBase 3F4BMNY7 on appropriate rates. What is difficult to gauge is the transfer time between the application buffer to the pc buffer. Unfortunately, the current method of running this application heavily relies on software operations. These software operations (starting & stopping task) are inherently non-deterministic due to the Windows OS. Your question (1) can be addressed by the above KB but the time that the data is written in the application is not deterministic. Question (2), should be neglible in this application since it’s within the nS range and most of the delay will be found in starting and stopping the task, which could reach mS.

There are ways around this, if you have the following hardware.
1) An additional device with counters. Upload all samples into the buffer. Import any counter, and use that as the sample clock to trigger the sample sets. Reference the Retriggerable Pulse Train Generation example for your sample clock. 
2) X Series Devices support retriggerable DO. Similarly to the above suggestion you can upload all the samples into memory and trigger each sample set. The device uses the DO Sample Clock signal to update the output with the next sample from the buffer. X Series also support retransmit mode, which implies that once all the samples have been sent it restarts.
3) HSDIO devices have scripting ability making this task much simpler. A script is a series of instructions that indicates how waveforms saved in the onboard memory should be sent. The script can specify the order in which the waveforms are generated, the number of times they are generated, and the triggers and markers associated with the generation.

Regards,
Glenn
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Thanks very much for your effort, Glenn. I have tried the code with 150K samples and the transfer (between our computer to PCI FIFO) takes about 50ms, which meets our needs already. 

 

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Hi Glenn,

I just get another question about a possible implementation: 

If we do not use internal on-board clock, instead we can have a timed external sample clock (say it is on for 50ms, then off for 50, then on for 50ms, etc) , then is it also OK to stack all the data on the FIFO (includes all pulse trains) and use such a external sample clock to determine when to start/stop?

Thanks again,

Kunyan

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Yes, this emulates my first suggestion that suggested using an external counter as a retiggerable sample clock. If you can control the sample block you can import all the data into the buffer.

Regards,
Glenn
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Yeah, I put an AND gate into the scb board and it works out nicely. Thanks again, Kunyan
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Hi Glenn,

 

Sorry to bother you again. I just hope to know more about the capability of this card that a question (maybe sounds naive) jump out of our mind: 

 

Suppose we have a long stack of data stored in on-board memo., which contains 10 sets of pulses (each with a duration of 10ms).

 

Running on the timed external clock mode, somehow during the experiment we want to output the first 5 sets,  and for next 5 sets we are running with previously unknown condition: depend on the experimental outcomes we have the following possibilities: 

 

case A: output pulse set No.7

case B: output pulse set No.9

...

 

Is there any tricks to shift the output pointer such that we can skip a few pulse sets and go directly (as quick as possible) to the desired pulse set? 

 

Regards,

Kunyan

 

 

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