12-09-2009 09:20 PM
Dear friends,
We are using PCI 6534 to do pattern output, software platforms are C++ and NIDAQmx.
The experimetal sequence is following:
(1) Output 400,000 samples (32-bit, so all channels are used) upon a trigger (start trigger);
Rate: 3MHz; so the total pattern output lasts about 50 ms; Internal on-baord clock;
(2) Wait for a few seconds, typically 5s;
(3) Output the next 400,000 samples (32-bit) upon a trigger; the sample here is different from that of setp (1);
(4) wait for a few seconds and output a new group of 32-bit 400,000 samples.
Now I have gone through the step (1), the code used are attached.
Do anyone have suggestions how to proceed?
Is it possible to load all the three groups of data array to the on-board FIFO, and use start-trigger and stop-trigger to start and stop the generation of three pulse groups?
Or is it possible to use the two on-board FIFOs, when the 1st FIFO is output, load data from PCI to the 2nd FIFOand wait, and so on...?
Thanks a lot!
Solved! Go to Solution.
12-10-2009 05:00 PM
12-14-2009 01:52 PM
12-14-2009 03:43 PM
Thanks a lot, Glenn. I kind of underatnd what you mean, but for firm check, I have attached the core part of the modified program, could you have a look at it briefly and see if that is what you meant?
I have two more questions regarding operation in this mode:
(1) Our data set includes sample size of 32-bit and sample numer 150,000. How long it would take to reload another set of samples to the on-board FIFO?
(2) For the hardware triggering, under this circumstance we need three Low-to-High triggers to initiate the three outputs, right? How long would be the delay between the trigger edge and the time when the actual output start?
12-15-2009 02:31 PM
12-15-2009 04:58 PM
Thanks very much for your effort, Glenn. I have tried the code with 150K samples and the transfer (between our computer to PCI FIFO) takes about 50ms, which meets our needs already.
12-16-2009 04:50 PM
Hi Glenn,
I just get another question about a possible implementation:
If we do not use internal on-board clock, instead we can have a timed external sample clock (say it is on for 50ms, then off for 50, then on for 50ms, etc) , then is it also OK to stack all the data on the FIFO (includes all pulse trains) and use such a external sample clock to determine when to start/stop?
Thanks again,
Kunyan
12-17-2009 11:22 AM
12-17-2009 05:15 PM
12-17-2009 05:34 PM
Hi Glenn,
Sorry to bother you again. I just hope to know more about the capability of this card that a question (maybe sounds naive) jump out of our mind:
Suppose we have a long stack of data stored in on-board memo., which contains 10 sets of pulses (each with a duration of 10ms).
Running on the timed external clock mode, somehow during the experiment we want to output the first 5 sets, and for next 5 sets we are running with previously unknown condition: depend on the experimental outcomes we have the following possibilities:
case A: output pulse set No.7
case B: output pulse set No.9
...
Is there any tricks to shift the output pointer such that we can skip a few pulse sets and go directly (as quick as possible) to the desired pulse set?
Regards,
Kunyan