How to calculate the execution time of a SCTL in FPGA VI?

[Rashid931]

Hi,

   Can anyone guide me that How to calculate the execution time of a SCTL for one iteration in FPGA VI?

Thanks and Regards,

Rashid

[ColeTrain · Accepted solution]

Hello Rashid,

A SCTL will always execute in one tick of the clock that it has been tied to.  So, if you are using a 40 MHz clock, that loop will execute in 25 ns.  If the code cannot complete in that, or if it requires two ticks of the clock to make the computation, your code will not compile, so you are guaranteed that this will always be how long it takes that piece of code to execute.

[Rashid931]

Hi ColeR,

    Thanks for your reply, As you said, the SCTL will execute in 25 ns for a 40 MHz clock. Then if I am using 25 MHz clock with SCTL in FPGA VI of PXIe-5641R, and I have to acquire 2048 samples of a signal, Then how much time it will take to complete the acquisition process? Will it be (1/25MHz)= 4nsec OR (2048/25MHz)=81.92 microsec?

Kindly reply.

Regards,

Rashid

[dsangree]

Rashid,

When doing acquisition you will be reading one I/Q pair per cycle giving you 81.92 microseconds to acquire all 2048 samples.

However, when you are outputting a signal with the 5641R, things are slightly different. The Digital to Analog converter takes alternating I and Q samples. This means that it takes two clock cycles per sample when doing output.

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@Rashid931 wrote:

Hi ColeR,

    Thanks for your reply, As you said, the SCTL will execute in 25 ns for a 40 MHz clock. Then if I am using 25 MHz clock with SCTL in FPGA VI of PXIe-5641R, and I have to acquire 2048 samples of a signal, Then how much time it will take to complete the acquisition process? Will it be (1/25MHz)= 4nsec OR (2048/25MHz)=81.92 microsec?

Kindly reply.

Regards,

Rashid

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