Efficient use of FPGA read/write

[jckvt]

I am writing a real-time application for a CompactRIO and I am looking for ways to simplify my code and reduce CPU usage. I use the FPGA to do a lot of CAN messaging and signal processing, then I have a VI running on the real time processor that reads values from the FPGA, does some processing and outputs data back to the FPGA. My code running on the real time utilizes many parallel running loops in a master/slave type architecture. One loop reads all needed info from the FPGA into indicators and writes values from controls to the FPGA. The other loops read the inputs and manipulate the outputs via local variables.

My question is would it be more efficient to get rid of the loop thats dedicated to FPGA communication and have each loop read and write to the FPGA directly. If I use one open FPGA reference block and use the output reference in multiple loops, will each read/write operation block the others until it is finished? Each output is only modified in one location in the code, but there are several inputs that are used by multiple loops. Is it still more efficient for each loop to read/write to the FPGA on demand? How will this affect determinism?

Thanks,

Jon 

[Robbob · Accepted solution]

Jon,

Read/Write controls will not be deterministic, but I believe your previous method should work just fine as long as you only have single writers. If you have multiple writers, you will start experiencing race conditions.

I don't believe you will see any noticable performance/CPU improvement in the alternate method. You would see large performance gains if your master loop reads slower of course, but that is always a tradeoff.