Vivado IP Locked error when building X41-X1_400

[Steven_R]

I am attempting to build an FPGA image, X410_X1_400. I have use branch "master" and "UHD-4.4". I am using Vivado v2021.1 with AR76780. Builds from both branches produce the bit file etc., but give the following error:

WARNING: [BD 41-1661] One or more IPs have been locked in the design 'x4xx_ps_rfdc_bd.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
x4xx_ps_rfdc_bd_cpld_jtag_engine_0

The "report IP status" output say that the IP definition is missing (or something to that effect). However, I can see the IP generated here:

user1@dev-machine2:~/repos/uhd/fpga/usrp3/top/x400$ ls -lr ./build-ip/xczu28drffvg1517-1e/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd/ip/x4xx_ps_rfdc_bd_cpld_jtag_engine_0/
total 104
-rw-rw-r-- 1 user1 user1 53576 Mar 29 14:38 x4xx_ps_rfdc_bd_cpld_jtag_engine_0.xml
-rw-rw-r-- 1 user1 user1 38846 Mar 29 14:38 x4xx_ps_rfdc_bd_cpld_jtag_engine_0.xci
drwxrwxr-x 2 user1 user1  4096 Mar 29 14:38 synth
drwxrwxr-x 2 user1 user1  4096 Mar 29 14:38 sim

The build.log is attached. I am able to program the X410 and probe it with uhd_usrp_probe. How can I correct this?

[Steven_R]

Adding the attachment.

[Steven_R · Accepted solution]

The following is a procedure from NI tech support which worked for me:

---

Please try these steps using UHD-4.6 and let me know if you still run into an issue:

1. In uhd/fpga/usrp3/top/x400, run "source setupenv.sh; make cleanall; make GUI=1 X410_X1_400".

2. After the GUI launches, wait until the build reaches the Synthesis state or later and cancel the build (you can also just wait for it to completely finish). Save the project.

3. Close the current project and open the saved project file.

4. Set the Hierarchy to "Automatic Update and Compile". See the image below.

5. Set the Implementation Strategy to "Performance_ExplorePostRoutePhysOpt".

6. Build the bitstream in the usual Vivado GUI flow. Note that the bitstream is not automatically copied to the build directory in the GUI build. You can find it at uhd/fpga/usrp3/top/x400/build-X410_X1_400/project_1/project_1.runs/impl/x4xx.bit.